摘要FPGA/CPLD是大规模集成电路技术发展的产物，是一种半定制的集成电路。它结合EDA技术可以快速、方便地构建数字系统。FPGA是电子设计领域中最具有活力和发展前途的一项技术。而本课题就是要基于FPGA实现通用异步串行接口。66205
UART（通用异步串行收发器）是一种短距离串行传输接口。论文使用VHDL硬件描述语言，利用QuartusII 7.0的综合描述，采用模块化设计方法设计UART的各个模块。其中包括：UART内核、波特率发生器、计数器、奇偶校验器、移位寄存器、总线选择器和信号监测器。本论文采用多模块的实现方法，从系统结构进行模块化分解，核心部分的UART内核采用了有限状态机。最后本论文对设计进行了编译和仿真，从仿真的结果可以看出，课题完成了基于FPGA实现通用异步串行接口的要求。
毕业论文关键词 FPGA VHDL语言 UART QuartusII 状态机
毕业设计说明书（论文）外文摘要
Title Realization of Universal Asynchronous Serial Interface Based on FPGA
Abstract
FPGA / CPLD is a product of the development of large scale integrated circuit technology. It is a semi-custom integrated circuits. It can build a digital system quickly and easily when combine it with the EDA technology.
FPGA is the most dynamic and promising technology in the electronic field. this project is to realize the universal asynchronous serial interface based on FPGA. UART (Universal Asynchronous serial transceivers) is a short-range serial transmission interface.Using VHDL hardware description language, the paper adopts modular design methods of UART modules with the comprehensive description of QuartusII 7.0. including: UART core, baudrate generator,counter,parity,shift registers,switch bus and detector.This thesis adopts multi-module implementations and uses modular decomposition from system structure, the core part of the UART core uses a finite state machine.Finally,this paper compiles the design and simulation.It can be seen from the simulation,subject has completed a universal asynchronous serial interface based on FPGA.
Keywords FPGA VHDL hardware description language UART QuartusII FSM
目 次
1. 引言 1
1.1 选题背景及意义 1
1.3 本文主要工作和组织安排 3
2. UART设计方法 4
2.1 UART协议背景 4
2.2 UART设计过程 4
2.3 实现技术与功能划分 7
3. UART子模块分析 9
3.1 信号监测器模块 9
3.2 移位寄存器模块 10
3.3 波特率发生器模块 12
3.4 计数器模块 15
3.5 总线选择器模块 17
3.6 奇偶校验器模块 18
3.7 UART内核模块 20
4 UART顶层模块及仿真分析 24
4.1 UART顶层模块 24
4.2 时序分析 VHDL+FPGA实现通用异步串行接口+代码:http://www.youerw.com/tongxin/lunwen_74024.html