DCM functional block is available in most digital FPGA devices。 It can implement a clock delay locked loop, a digital frequency synthesizer and digital phase shifter。 Here, DCM shifts the clock phase optionally to delay the incoming clock by a fraction of the clock period。 For instance shown in Fig。 6, the DCM pides the incoming clock FCLK (50% ratio) into four equal clocks clk_0, clk_90, clk_180 and clk_270 respectively, then the four phase-shifted clocks can act as an equivalent 22·FCLK clock with a 4:1 multiplexer。 Thus, the clock frequency for the DCM architecture can be reduced by 22 times for a fixed-resolution DPWM or the resolution can be increased by 2 bits for a fixed-frequency DPWM。 Since the relationship between system clock FCLK, hardware DPWM resolution NDPWM and switching frequency fs can be written as:
FCLK = 2NDPWM ⋅ fs 。 (12)
Then the required clock FDCM for the four-phase-shift DCM module can be expressed as:
FDCM = FCLK ⋅2(NDCM −2) =[2(NDPWM +NDCM −2)]⋅ fs , (13)
where NDCM is the bit number of DPWM implemented by four-phase-shift DCM module。
A segmented DCM phase-shift architecture including two 2-bit DCM phase-shift modules in series is introduced in [12]。 The similar segmented DCM architecture is also employed as a 4-bit DPWM block in this paper。 Since the proposed DPWM includes a 2-bit counter-comparator, the hardware clock frequency is FCLK=22·fs。 According to (13), the incoming clock frequency FDCM for the segmented DCM module is FDCM=FCLK ·2(4–2)=22·FCLK。 The structure diagram of the 4-bit segmented DCM phase-shift block is shown in Fig。 7, which mainly includes DCM-4x with function of quadrupling frequency, DCM-I and DCM-II。 On the one
Fig。 7。 Structure diagram of 4 bit segmented DCM phase-shift block。
hand, the input clock FCLK propagates in zero delay through DCM-4x, and then the first phase shifted versions, PX0, PX90, PX180 and PX270 are generated by DCM-I in this case。 On the other hand, the clock FDCM, four times as high as the incoming clock FCLK, is operated at DCM-II, and further phase shifted signals of the clock , PY0, PY90, PY180 and PY270 are produced。 As observed from Fig。 7, the resolution is now increased by 16 times without increasing the whole system hardware clock frequency by 16 times。
Using two 4:1 multiplexers to select the corresponding shifted clock signals, the whole block realizes D[3:0] which is the 4 LSBs of DPWM duty D[5:0] from MASH ∆-Σ block。 Depending on duty ratio D[3:2], S1 can be derived from one of the four phase-shifted clock signals PX0, PX90, PX180 and PX270。 Then S1 acts as an equivalent clock of four times (x4) the phase-shifted signals。 Similarly, duty ratio D[1:0] selects one of the four phase-shifted clock signals PY0, PY90, PY180 and PY270 for S2 which acts an equivalent clock of four times (x4) the phase-shifted signals。 Then the two selected signals are operated in logic AND circuit to generate the final phase-shift signal Sc whose frequency is 16 times (double x4) as high as the incoming clock FCLK and will be sent to counter-comparator。 The most attractive merit of this segmented DCM phase-shift architecture is that the final output signal Sc has 24 kinds of clock possibilities during each of FCLK clock cycle, where S1 has 22 kinds of “coarse” phase-shift and S2 has 22 kinds of “fine” phase-shift。 Thus, this segmented DCM block can either increase 4-bit DPWM resolution (for fixed fs) or reduce the clock frequency by 24 times (for fixed NDPWM)。 The logic waveforms of the 4-bit segmented DCM phase-shift operation are shown in Fig。 8。
C。 2-bit counter-comparator block 高频低功耗直流-直流开关电源英文文献和中文翻译(4):http://www.youerw.com/fanyi/lunwen_101038.html