system operating  speed.
2.  Economics  of IC  Testing
2.1.  Introduction
There are many different test strategies for testing  in-
tegrated circuits. These vary from using no structured
DFT  approach,  relying on  good  design  practice  and
experts to generate an effective  test, to adopting a single
structured DFT approach  [5]. These approaches have
proven valuable and  cost effective in many  scenarios.
However, whereas one method has  proven to be  eco-
nomically viable for one company it is not guaranteed
to  be  so  for  another.  Indeed,  what  has  proven  to  be
economical for one design might not be economic for
another within  the  same  company.
As the complexity of  devices and the variety of  struc-
tured partitions of a  chip increase there are more and
more DFT approaches that could be used. For example,
in many complex devices an effective  test strategy can
be obtained from a mixture of ad hoc methods,  struc-
tured DFT and Built-in Self-Test (BIST). This adds  to
the complexity and permutations of what can be used.
For example,  the number of BIST methods  for an
embedded  PLA  is  greater  than  20  [6].  Each  BIST
method will have a  different effect on area overhead,
test length/time, I/O requirement, fault cover, and per-
formance. The relative importance of these character-
istics for each BIST method will change depending on
the PLAfs functionality and size, number of devices to
be tested,  and also on  the  skill of the designer and/or
effectiveness  of  the  design  tools.  Thus  it  would  be
unreasonable to expect a designer to identify  the "best"
test met.hod for each embedded PLA in the design. Fur-
thermore,  as we need to minimize the overall design, manufacture, and  test costs  for the device, our  selec-
tion  procedure  for  the  "best"  DFT  method  for  the
embedded  PLA  needs  to  consider  what  other  DFT
methods are being adopted for other partitions of the
device.
2.2.  The ECOtest System
The  ECOtest  System,  a  tool  developed  by  Brunel
University in collaboration with Siemens-Nixdorf  In-
formationssysteme,  is a test strategy planning  tool utiliz-
ing economics modeling for cost optimal selection of
DFT methods  [7]-[10].
The ECOtest System was developed specifically  for
the design of ASICs. Chips are fabricated by external
vendors, who also test them with test patterns supplied
by the designers. This definition  of  the application area
of  the test strategy planner affects  the design of  the cost
model.  It  thus  highlights  the  specific  nature  of  the
economic results that will be presented later in this ar-
ticle.  For  example,  the  fact  that  an  external  vendor
fabricates the chips means that the cost of production
can be easily calculated from the vendors prices,  if a
good  estimation of gate count  can be  achieved.
The  structure  of the ECOtest  System can be  seen
in Figure 2.
The design description is acquired either from the
user or  from an existing netlist and is built in a hier-
archical fashion  in order to allow  test strategy decisions ECO测试系统英文文献和中文翻译(3):http://www.youerw.com/fanyi/lunwen_8050.html