Table 1: The Bit Definition in PWMCON
BIT Description
TF4 Interrupt Request for PWM0
TR4 RUN bit for PWM0
TF3 Interrupt Request for PWM1
TR3 RUN bit for PWM1
PSEL Channel Select in
Complementary Mode
CPWM Mode Select
T4M Clock Prescaler for PWM1
T3M Clock Prescaler for PWM0
2.2.2 Channel-select logic
The follow Fig. 5 shows the channel-select logic which is useful in Complementary Mode. From this diagram, it is clear to know that signal CP and CPWM control the source of PWMH and PWML. And the details about the two control signals will be discussed in the section 3, and the architecture of dead-time generator will also be discussed in section 3.1 for the continuity of Complementary Mode.
Fig. 5 Diagram of Channel-select Logic
3. Operation Mode and Simulation Results
The design has two operation modes: Independent Mode and Complimentary Mode. By setting the corresponding bit CPWM in register PWMCON shown in Fig. 4, user can select one of the two operation modes. When CPWM is set to zero,PWM module will work in Independent Mode, whereas,PWM module will work in Complimentary Mode. In the following of this section, the two operation mode will be explained respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which verify the design will also be shown.
3.1 Independent PWM Output Mode
An Independent PWM Output mode is useful for driving loads such as the one shown in Figure 1. A particular PWM output is in the Independent Output mode when the corresponding CP bit in the PWMCON register is set to zero.In this case, two-channel PWM outputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0 generator, and the signal on pin PWM1/PWML is from PWM0 generator. The separate case is achieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set to independent mode by default upon advice reset. The dead-time generator is disabled in the Independent mode. The simulation result is shown in Figure 4 as the following Fig.5.Tr4 and tr3 are run bits to PWM0 and PWM1, respectively.Actually, from this diagram, Pin P1[5]/ P1[4] of MCU is used for PWMH/ PWML or normal I/O ,alternatively.
Fig.6 the Waveform of PWM Outputs in Independent Mode
3.2 Complementary PWM Output Mode
The Complementary Output mode is used to drive inverter loads similar to the one shown in Figure 7. This inverter topology is typical for DC applications. In Complementary Output Mode, the pair of PWM outputs cannot be active simultaneously. The PWM channel and output pin pair are internally configured through channel-select logic as shown in Figure 5. A dead-time may be optionally inserted during
device switching where both outputs are inactive for a short period.Authorized licensed use limited to: East China Normal University. Downloaded on January 11, 2009 at 00:36 from IEEE Xplore. Restrictions apply.Proceedings of HDP’07 优-文^论'文.网http://www.youerw.com
The Complementary mode is selected for PWM I/O pin pair by setting the appropriate CPWM bit in PWMCON. In this case, PSEL is in effect. PWMH and PWML will come from PWM0 generator when PSEL is set to zero, when the signals from PWM1 generator is useless, whereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1, when the signals from PWM0 generator is useless. In the process of producing the PWM outputs in Complementary Mode, the dead-time will be inserted to be discussed in the following section.
Fig 7: Typical Load for Complementary PWM Outputs
3.3 Dead-time Control
Dead-time generation is automatically enabled when PWM I/O pin pair is operating in the Complementary Output mode. Because the power output devices cannot switch
instantaneously, some amount of time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other
transistor. The 2-output PWM module has one programmable dead-time with 8-bit register.The complementary output pair for the PWM module has an 8-bit down counter that is used to produce the dead-time insertion. As shown in Figure 8, the dead time unit has a rising and falling edge detector connected to PWM signal
from one of PWM generator. The dead times is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts
down to zero. A timing diagram indicating the dead time insertion for the pair of PWM outputs is shown in Figure 8.
Fig.8 Dead-time Unit Block Diagram
Conclusions
In this paper, we have designed PWM module based on an 8-bit MCU compatible with 8051 family. The design can generate 2-channel programmable periodic PWM signals with two operation mode, Independent Mode and Complementary Mode in which dead-time will be inserted. The simulation results on the EDA platform have proven its correctness andusefulness.
Acknowledgments
The authors would like to thank Shanghai Leading Academic Discipline Project (Project Number: T0103) for the financial support.